1. Field of the Invention
The present invention relates to a method of producing large-area membrane masks.
For electron and ion projection lithography as well as X-ray lithography it is necessary to produce membrane masks having a thickness in the micrometer range and a membrane area up to more than 100 square centimeters. The membrane masks produced in correspondence with the inventive method may be applied in general for lithographic methods operating on charged particles and photons. One example is the application in 157 nm lithography. Equally, an application for masking out neutral particles (atomic lithographic) and in all applications operating on vacuum evaporation masks is possible. Membrane masks as the product of a method according to the present invention are generally also suitable for use with sensors.
2. Prior Art
Starting out from silicon wafers as substrate material two different approaches are pursued in an industrial process for producing the membrane masks. They are fundamentally distinguished by the aspect whether the process steps for structuring the masks are performed before or after the production of the membrane.
In the so-called xe2x80x9cmembrane flow processxe2x80x9d, which is represented, for instance, in the U.S. Pat. No. 5,110,373, first the membrane is produced and all the steps of process for generating the mask structures are carried out on the membrane. The disadvantage of this sequence of process steps consists in the fact that the highly critical steps of mask structuring take place on a comparatively unstable membrane.
In the so-called xe2x80x9cwafer flow processxe2x80x9d, which is disclosed, for instance, in the PCT application WO 97/43694, first the mask structures are generated on a compact silicon wafer and the membrane production takes place at the end of the mask process. The critical aspect in this process flow consists in the fact that during membrane etching no or only reproducible modifications may occur on the mask structures already existing.
In accordance with the U.S. Pat. No. 5,110,373 and the PCT application WO 97/43694 the conventional electrochemical etching stop technique with a so-called PN etching stop is employed.
All these processes of membrane mask production involve the aggravating problem that, on the one hand, the membrane must present a certain tensile stress for constituting a plane surface in a very stable manner, whilst, on the other hand, this tensile stress must be kept as low as possible because it leads inevitable to deformations of the mask structures and problems in terms of service life.
Here the wafer flow process entails clear advantages because there is fundamentally the possibility to operate on very low tensile stress levels of the membrane layer as the structuring process for the mask structures takes place on the stable wafer rather than on the membrane. However, this process gives also rise to very high demands on the membrane etching process.
The subject matter of the invention are process flows for membrane etching in the waver flow process, with the example which will be described in the following starting out from a process employing SOI (silicon on insulator) silicon wafers, as it is used for the production of so-called stencil masks. In this context reference should be made to the publication by Yoshinori Nakayama, Yasunari Sohda, Norio Saitou and Hiroyuki Itoh, entitled xe2x80x9cHighly accurate calibration method of electronbeam cell projection lithographyxe2x80x9d, in: SPIE vol. 1924 (1993), pages 185 and 190, on the SPIE Conference 1993. Stencil marks and membrane masks having opened structures in the membrane layer. The inventive solutions disclosed with reference to the SOI wafer flow process do not preclude, however, their potential application also for other waver flow or membrane flow processes.
FIG. 1 illustrates the most essential process steps of an SOI wafer flow process according to prior art:
1A SOI silicon wafer as original material, with the 2-3 xcexcm thick silicon layer (1) forming the subsequent membrane layer on the upper side, which is insulated from the 500 to 600 xcexcm thick compact silicon wafer (3) by a dielectric layer (2), e. g. silicon dioxide with a thickness of 200 to 400 nm,
1B application of a masking layer (4) on the upper side and a masking layer (5) on the underside of the silicon wafer,
1C structuring the masking structures on the upper side by means of lithographic processes for producing a photoresist mask (6) and subsequent plasma etching of the masking layer (4),
1D trench etching of the masking structures in the silicon layer (1) on the upper side, which has a thickness of 2-3 xcexcm, and removal of the photoresist mask (6),
1E lithographic masking (7) and etching of a window into the masking layer (5) on the underside of the silicon wafer,
1F removal of the photoresist mask (7) for rear-side windows,
1G membrane etching process, i.e. removal of the compact silicon wafer (3) in the masked window zone (8),
1H stripping of the masking layers (4), (5) and the insulating layer (2) in the membrane region.
The membrane etching step is generally performed in anisotropic, wet chemical etching processes, e. g. using an aqueous KOH or TMAH (tetra methyl ammonium hydroxide) solution as etching agent.
The etching stop is performed on the insulating layer, but only with a restricted selectivity. As for reasons of mechanical strain the insulating layer must be kept as thin as possible and as a result of the restricted selectivity thereof the etching stop is very critical.
During the etching process, which takes a corresponding number of hours at silicon etching rates of 30-40 xcexcm/h, the structured membrane side must be definitely reliably protected from any etching corrosion. In this operation measures must be taken to ensure that the agents used for protection of the membrane side can be removed again without any residues at the end of the process and that no geometric modifications occur on the structures in the membrane layer on account of both the protective agent and the removal thereof.
In correspondence with prior art a very reliable method is available for sealing all regions on the Si wafer outside of the window that is opened on the rear side, in other words the integration of an etching cell with seals, which are mechanically pressed against the system.
The disadvantage of such a solution consists in the aspect that there is a very high risk of breaking at the end of the etching process, i.e. at a time by which the membrane region approaches its final thickness of a few millimeters. The main cause thereof are distorsions induced by the mechanical sealing of the cell, particularly also for the reason that additional thermal distorsions occur in the etching bath which has a temperature of at least 60xc2x0 C.
Moreover, it is unavoidable that during the handling of the cell and specifically in the etching bath a difference in pressures occurs between the interior of the cell and the environment, which acts upon the membrane and is inclined to destroy the latter easily.
Finally, the highly sensitive membrane must be withdrawn from the comparatively robust cell, which is equally a very critical step of the process.
Another approach consists in covering the membrane side with a protective layer presenting all the properties mentioned already, such as a sufficient resistance to etching and the possibility of removal without residues and without any influence on the membrane structures. Apart therefrom, this layer, too, may give rise to slight mechanical tensions only in the membrane/protective layer system so as to avoid any destruction of the membrane mask as early as before or during its removal.
The difficulty involved in this approach consists in the problem that to date protective layers cannot be found which satisfy all these requirements at the same time.
The present invention is based on the problem of providing methods of producing large-area membrane masks, wherein an inexpedient mechanical excessive strain or deformations of the membrane or of the membrane layer/etching stop layer/supporting wafer system, respectively, which occurs particularly as a result of the use of an etching cell or generally as a result of the thin semiconductor layers, or any resulting breaking of the components in the respective steps of method is or are avoided.
The two-step method entails additional advantages in the selection of the etching media because different etching media may be used in the first and second steps. These two etching media may be different etching agents or only different concentrations or temperatures of the same etching agent. With the etching process being stopped at a silicon dioxide layer in the SOI wafer flow process, which layer must be as thin as possible for reasons of mechanical strain, a high selectivity in etching is required. For this reason it is recommendable to perform the second etching step in this case with TMAH while the first step may be carried out in a KOH bath.
Another possibility, which derives from the two-step method, consists in the realisation of the first step as a step of dry etching in plasma.
The protective coating may be expediently configured as dielectric layer or polymer layer in correspondence with the mechanical and chemical requirements.
Moreover, the etching selectivity of the second step relative to the stop layer and the protective layer may be optimised for optimum, particularly complete, removal of the semiconductor support layer without any excessive corrosion of the stop and protective layer.
The two-step method hence offers numerous possibilities of optimisation in terms of the etching rate (productivity, costs) and selectivity (yield) of the membrane etching process (i.e. removal of the semiconductor support layer).
For both inventive methods furthermore possibilities are available for optimisation of the stop layer as such in view of the demands on the mechanical properties as well as for adaptation of the etching process to the respective stop layer. The stop layer can hence expediently consist of a dielectric layer, a metal layer, a polymer layer or a combination of layers. A sufficient selectivity of the stop layer is an important criterion of optimisation, too.
Hence the mechanical strain on the membrane layer/etching stop layer/supporting wafer system cannot only be expediently managed but the two-step process permits in particular a selective optimisation of the mechanical strain on the membrane layer.
This may be a great advantage for both the geometric stability of the membrane mask and the accuracy of the mask structures in terms of structure and position, which us dependent thereon.
The layer or the combination of layers, respectively, may also be expediently optimised with respect to a defined conductivity in correspondence with the desired applications.
In accordance with the inventive methods the mechanical strain on the membrane may be expediently varied within wide limits from compressive strain to tensile stress by an appropriate matching of the removal of the semiconductor support layer.
By doping the membrane layer on the supporting wafer it is possible to vary the mechanical strain on the membrane mask from compressive strain to tensile stress over a wide range. The SOI wafer flow process as described in the embodiment is particularly well appropriate for this purpose. The dielectric layer causes the etching stop independently of the doping level of the silicon layer disposed thereon. It is thus possible to dope the silicon layer at option, i.e. exclusively in the sense of an optimum membrane tension.
The application of the SOI technology presents further advantages over the conventional electrochemical etching stop technique, such as the advantages that the method is simplified and its efficiency is improved, that hence the yield is increased and that the method can be performed at lower costs.
The conventional electrochemical etching stop technique permits only a method operating on an etching cell, with etching being possible only in a single step. Moreover, only comparatively small membranes are conventionally manufactured.
With the masking layer being structured for etching of the semiconductor support layer being performed as a first step of the method or as part of the manufacture of the original material for the semiconductor wafer, any faults occurring in this process cannot result in a rejection of parts which have already incurred substantial costs, which is another advantage. Hence costs are reduced by this expedient embodiment of the method.
The invention will be described in the following by exemplary embodiments, with reference to the drawing, without any restriction of the general inventive idea, to which drawing explicit reference is made in all other respects as far as the disclosure of all inventive details is concerned which are not explained completely in the text. The inventive solutions described for the example of the SOI wafer flow process do not preclude their potential application also for other wafer flow or membrane flow processes.